3742 search results - page 418 / 749 » On the Use of Formal Techniques for Validation |
208
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TOMACS
1998
15 years 6 months ago
1998
architectures at multiple levels of abstraction, encompassing both hardware and software. It has five modes of operation (Design, Model Validation, Build Simulation, Simulate Syste...
209
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FIDJI
2003
Springer
15 years 12 months ago
2003
Springer
The popular slogan ”write once, run anywhere” effectively renders the expressive capabilities of the Java programming framework for developing, deploying, and reusing target-i...
181
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SPIN
2007
Springer
16 years 25 days ago
2007
Springer
d Abstract) Luboˇs Brim and Jiˇr´ı Barnat Faculty of Informatics, Masaryk University, Brno, Czech Republic With the increase in the complexity of computer systems, it becomes e...
204
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BMCBI
2004
15 years 6 months ago
2004
Background: Microarray experiments are becoming a powerful tool for clinical diagnosis, as they have the potential to discover gene expression patterns that are characteristic for...
228
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DLT
2009
15 years 4 months ago
2009
Abstract. Temporal logics are a well investigated formalism for the specification and verification of reactive systems. Using formal verification techniques, we can ensure the corr...