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151
Voted
DATE
2007
IEEE
16 years 1 months ago
2007
IEEE
Errors in timing closure process during the physical design stage may result in systematic silicon failures, such as scan chain hold time violations, which prohibit the test of ma...
183
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IFIP
2004
Springer
16 years 3 days ago
2004
Springer
Ensuring correctness of software by formal methods is a very relevant and widely studied problem. Automatic verification of software using model checkers from the state space exp...
147
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DAC
2010
ACM
15 years 10 months ago
2010
ACM
Timing exception verification has become a center of interest as incorrect constraints can lead to chip failures. Proving that a false path is valid or not is a difficult problem ...
204
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DAWAK
2006
Springer
15 years 8 months ago
2006
Springer
Abstract. Data warehouses (DW) main objective is to facilitating decisionmaking. Thus their development has to take into account DW project actor requirements. While much recent re...
222
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SEBD
2003
15 years 8 months ago
2003
The Ambient Logic is a modal logic proposed to describe the structural and computational properties of distributed and mobile computations. The static part of the Ambient Logic is,...