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» On the Use of Formal Techniques for Validation
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FORMATS
2004
Springer
15 years 10 months ago
Decomposing Verification of Timed I/O Automata
This paper presents assume-guarantee style substitutivity results for the recently published timed I/O automaton modeling framework. These results are useful for decomposing verifi...
Dilsun Kirli Kaynar, Nancy A. Lynch
ISOLA
2010
Springer
15 years 5 months ago
Worst-Case Analysis of Heap Allocations
In object oriented languages, dynamic memory allocation is a fundamental concept. When using such a language in hard real-time systems, it becomes important to bound both the worst...
Wolfgang Puffitsch, Benedikt Huber, Martin Schoebe...
FORMATS
2010
Springer
15 years 4 months ago
Robust Satisfaction of Temporal Logic over Real-Valued Signals
Abstract. We consider temporal logic formulae specifying constraints in continuous time and space on the behaviors of continuous and hybrid dynamical system admitting uncertain par...
Alexandre Donzé, Oded Maler
ICSR
2009
Springer
16 years 1 months ago
Introducing Motivations in Design Pattern Representation
Abstract. Design pattern formalization is aimed at encouraging the use of design patterns during the design phase. Many approaches focuses on providing solutions with a graphical n...
Luca Sabatucci, Massimo Cossentino, Angelo Susi
SEMWEB
2007
Springer
16 years 23 days ago
Logical Foundations of (e)RDF(S): Complexity and Reasoning
Abstract. An important open question in the semantic Web is the precise relationship between the RDF(S) semantics and the semantics of standard knowledge representation formalisms ...
Jos de Bruijn, Stijn Heymans