3742 search results - page 291 / 749 » On the Use of Formal Techniques for Validation |
155
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ISVLSI
2007
IEEE
16 years 28 days ago
2007
IEEE
Formal verification has become an important step in circuit and system design. A prominent technique is Bounded Model Checking (BMC) which is widely used in industry. In BMC it i...
194
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WETICE
2000
IEEE
15 years 11 months ago
2000
IEEE
A better understanding of how groupware systems have been evaluated in the past can help to frame the discussion of what methods and techniques should be considered for future eva...
158
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AOSE
2000
Springer
15 years 11 months ago
2000
Springer
Abstract. The agent paradigm can be seen as an extension of the notion of (active) objects by concepts like autonomy, cooperation, and goal-oriented behavior. Mainstream object-ori...
152
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ICFEM
2009
Springer
16 years 1 months ago
2009
Springer
Formal specification languages are traditionally supported by theorem provers, but recently model checkers have proven to be useful tools. In this paper we present Eboc, an explic...
147
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SAS
2007
Springer
16 years 23 days ago
2007
Springer
Abstract. Pointer information is a prerequisite for most program analyses, and inclusion-based, i.e. Andersen-style, pointer analysis is widely used to compute such information. Ho...