Sciweavers

3742 search results - page 287 / 749
» On the Use of Formal Techniques for Validation
Sort
View
PATMOS
2007
Springer
16 years 23 days ago
Soft Error-Aware Power Optimization Using Gate Sizing
—Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the...
Foad Dabiri, Ani Nahapetian, Miodrag Potkonjak, Ma...
TCAD
2008
172views more  TCAD 2008»
15 years 6 months ago
General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...
Foad Dabiri, Ani Nahapetian, Tammara Massey, Miodr...
189
Voted
HICSS
2005
IEEE
142views Biometrics» more  HICSS 2005»
16 years 8 days ago
Integrated Optimization and Multi-Agent Technology for Combined Production and Transportation Planning
In this research project, an integration of multi-agent technology and optimization techniques is suggested for the combined production and transport planning problem in a transpo...
Jan A. Persson, Paul Davidsson
DAC
1999
ACM
15 years 11 months ago
Circuit Complexity Reduction for Symbolic Analysis of Analog Integrated Circuits
This paper presents a method to reduce the complexity of a linear or linearized (small-signal) analog circuit. The reduction technique, based on quality-error ranking, can be used...
Walter Daems, Georges G. E. Gielen, Willy M. C. Sa...
VLDB
1990
ACM
106views Database» more  VLDB 1990»
15 years 10 months ago
The Time Index: An Access Structure for Temporal Data
In this paper, we describe a new indexing technique, the time indez, for improving the performance of certain classes of temporal queries. The time index can be used to retrieve v...
Ramez Elmasri, Gene T. J. Wuu, Yeong-Joon Kim