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» On the Use of Formal Techniques for Validation
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DATE
1999
IEEE
123views Hardware» more  DATE 1999»
15 years 11 months ago
Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs
This paper reports a formal methodology for verifying a broad class of synthesized register-transfer-level (RTL) designs by accommodating various register allocation/optimization ...
Nazanin Mansouri, Ranga Vemuri
ZUM
2000
Springer
15 years 10 months ago
A Computation Model for Z Based on Concurrent Constraint Resolution
We present a computation model for Z, which is based on a reduction to a small calculus, called Z, and on concurrent constraint resolution techniques applied for computing in thi...
Wolfgang Grieskamp
PTS
2000
99views Hardware» more  PTS 2000»
15 years 7 months ago
Verification of Test Suites
We present a formal approach to check the correctness and to propose corrections of hand-written test suites with respect to a formal specification of the protocol implementations ...
Claude Jard, Thierry Jéron, Pierre Morel
KSEM
2010
Springer
15 years 4 months ago
Large-Scale, Exhaustive Lattice-Based Structural Auditing of SNOMED CT
One criterion for the well-formedness of ontologies is that their hierarchical structure forms a lattice. Formal Concept Analysis (FCA) has been used as a technique for assessing ...
Guo-Qiang Zhang
FMCO
2009
Springer
130views Formal Methods» more  FMCO 2009»
15 years 4 months ago
Interleaving Symbolic Execution and Partial Evaluation
Partial evaluation is a program specialization technique that allows to optimize programs for which partial input is known. We show that partial evaluation can be used with advanta...
Richard Bubel, Reiner Hähnle, Ran Ji