3742 search results - page 185 / 749 » On the Use of Formal Techniques for Validation |
149
click to vote
VLSID
2004
IEEE
16 years 6 months ago
2004
IEEE
The detection of all open defects within 6T SRAM cells is always a challenge due to the significant test time requirements. This paper proposes a new design-for-test (DFT) techniq...
129
click to vote
ASPDAC
2006
ACM
16 years 13 days ago
2006
ACM
— We present an efficient method for automatically extracting unified amplitude/phase macromodels of arbitrary oscillators from their SPICE-level circuit descriptions. Such com...
209
click to vote
VLSID
2004
IEEE
16 years 6 months ago
2004
IEEE
This paper presents a novel technique for abstracting designs in order to increase the efficiency of formal property checking. Bounded Model Checking (BMC), using Satisfiability (...
246
click to vote
CORR
2010
Springer
15 years 5 months ago
2010
Springer
Graphs and graph transformation systems are a frequently used modelling technique for a wide range of different domains, covering areas as diverse as refactorings, network topolog...
204
click to vote
FM
2003
Springer
15 years 11 months ago
2003
Springer
We present a semantics for fault tree analysis, a technique used for the analysis of safety critical systems, in the real-time interval logic Duration Calculus with Liveness and sh...