3742 search results - page 160 / 749 » On the Use of Formal Techniques for Validation |
151
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MICRO
2008
IEEE
15 years 6 months ago
2008
IEEE
Verification of chip multiprocessor memory systems remains challenging. While formal methods have been used to validate protocols, simulation is still the dominant method used to ...
163
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DAC
2006
ACM
16 years 12 days ago
2006
ACM
Architectural decisions for DSP modules are often analyzed using high level C models. Such high-level explorations allow early examination of the algorithms and the architectural ...
126
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ISCAS
1995
IEEE
15 years 10 months ago
1995
IEEE
This paper presents an analysis technique that can be used to compute the harmonic and intermodulation distortion levels of a sampled-data circuit directly from a SPICE transient ...
158
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DSD
2009
IEEE
15 years 10 months ago
2009
IEEE
This paper addresses the design issue of System-onelevating the design abstraction levels, through a model-driven approach. It considers the standard Marte profile, which is dedic...
184
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ENTCS
2006
15 years 6 months ago
2006
The AVISPA Tool is a push-button tool for the Automated Validation of Internet Security Protocols and Applications. It provides a modular and expressive formal language for specif...