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» On the Use of Formal Techniques for Validation
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ISQED
2011
IEEE
230views Hardware» more  ISQED 2011»
14 years 10 months ago
Constraint generation for software-based post-silicon bug masking with scalable resynthesis technique for constraint optimizatio
Due to the dramatic increase in design complexity, verifying the functional correctness of a circuit is becoming more difficult. Therefore, bugs may escape all verification effo...
Chia-Wei Chang, Hong-Zu Chou, Kai-Hui Chang, Jie-H...
AMAI
2000
Springer
15 years 10 months ago
Using topology for spatial reasoning
Several formalisms have been proposed for qualitative reasoning about regions and their topological relations in space. These formalisms, based on pairwise relations, do not allow...
Boi Faltings
EMSOFT
2005
Springer
15 years 12 months ago
Using separation of concerns for embedded systems design
systems are commonly abstracted as collections of interacting components. This perspective has lead to the insight that component behaviors can be defined separately from admissi...
Ethan K. Jackson, Janos Sztipanovits
FM
2009
Springer
138views Formal Methods» more  FM 2009»
16 years 28 days ago
What Can Formal Methods Bring to Systems Biology?
This position paper argues that the operational modelling approaches from the formal methods community can be applied fruitfully within the systems biology domain. The results can ...
Nicola Bonzanni, K. Anton Feenstra, Wan Fokkink, E...
JACM
2002
163views more  JACM 2002»
15 years 6 months ago
Formal verification of standards for distance vector routing protocols
We show how to use an interactive theorem prover, HOL, together with a model checker, SPIN, to prove key properties of distance vector routing protocols. We do three case studies: ...
Karthikeyan Bhargavan, Davor Obradovic, Carl A. Gu...