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» On the Structure of Low Sets
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ICCD
2006
IEEE
117views Hardware» more  ICCD 2006»
16 years 3 months ago
Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address Buses
— The influence of interconnects on processor performance and cost is becoming increasingly pronounced with technology scaling. In this paper, we present a fast compression sche...
Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Maha...
GLOBECOM
2009
IEEE
16 years 1 months ago
Sparse Decoding of Low Density Parity Check Codes Using Margin Propagation
—One of the key factors underlying the popularity of Low-density parity-check (LDPC) code is its iterative decoding algorithm that is amenable to efficient hardware implementati...
Ming Gu, Kiran Misra, Hayder Radha, Shantanu Chakr...
ISVLSI
2007
IEEE
184views VLSI» more  ISVLSI 2007»
16 years 20 days ago
Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction
As power consumption of the clock tree dominates over 40% of the total power in modern high performance VLSI designs, measures must be taken to keep it under control. One of the m...
Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
EUROCRYPT
2007
Springer
16 years 16 days ago
Atomic Secure Multi-party Multiplication with Low Communication
We consider the standard secure multi-party multiplication protocol due to M. Rabin. This protocol is based on Shamir’s secret sharing scheme and it can be viewed as a practical ...
Ronald Cramer, Ivan Damgård, Robbert de Haan
ESCIENCE
2006
IEEE
16 years 13 days ago
Characterization of Computational Grid Resources Using Low-Level Benchmarks
An important factor that needs to be taken into account by end-users and systems (schedulers, resource brokers, policy brokers) when mapping applications to the Grid, is the perfo...
George Tsouloupas, Marios D. Dikaiakos