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» On the Representation of Timed Polyhedra
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ASPDAC
2009
ACM
152views Hardware» more  ASPDAC 2009»
16 years 1 months ago
A novel Toffoli network synthesis algorithm for reversible logic
—Reversible logic studies have promising potential on energy lossless circuit design, quantum computation, nanotechnology, etc. Reversible logic features a one-to-one input outpu...
Yexin Zheng, Chao Huang
CASES
2009
ACM
16 years 1 months ago
Tight WCRT analysis of synchronous C programs
Accurate estimation of the tick length of a synchronous program is essential for efficient and predictable implementations that are devoid of timing faults. The techniques to dete...
Partha S. Roop, Sidharta Andalam, Reinhard von Han...
DATE
2006
IEEE
158views Hardware» more  DATE 2006»
16 years 18 days ago
Modeling multiple input switching of CMOS gates in DSM technology using HDMR
Abstract— Continuing scaling of CMOS technology has allowed aggressive pursuant of increased clock rate in DSM chips. The ever shorter clock period has made switching times of di...
Jayashree Sridharan, Tom Chen
CIKM
2005
Springer
16 years 2 days ago
Optimizing candidate check costs for bitmap indices
In this paper, we propose a new strategy for optimizing the placement of bin boundaries to minimize the cost of query evaluation using bitmap indices with binning. For attributes ...
Doron Rotem, Kurt Stockinger, Kesheng Wu
ECAI
2004
Springer
15 years 12 months ago
IPSS: A Hybrid Reasoner for Planning and Scheduling
In this paper we describe IPSS (Integrated Planning and Scheduling System), a domain independent solver that integrates an AI heuristic planner, that synthesizes courses of actions...
María Dolores Rodríguez-Moreno, Ange...