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» On the Processing of Decimated Signals
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ICCD
2004
IEEE
138views Hardware» more  ICCD 2004»
16 years 3 months ago
Design and Implementation of Scalable Low-Power Montgomery Multiplier
In this paper, an efficient Montgomery multiplier is introduced for the modular exponentiation operation, which is fundamental to numerous public-key cryptosystems. Four aspects a...
Hee-Kwan Son, Sang-Geun Oh
ICCD
2002
IEEE
160views Hardware» more  ICCD 2002»
16 years 3 months ago
Modeling Switching Activity Using Cascaded Bayesian Networks for Correlated Input Streams
We represent switching activity in VLSI circuits using a graphical probabilistic model based on Cascaded Bayesian Networks (CBN’s). We develop an elegant method for maintaining ...
Sanjukta Bhanja, N. Ranganathan
ICCAD
2008
IEEE
127views Hardware» more  ICCAD 2008»
16 years 3 months ago
Verification of arithmetic datapaths using polynomial function models and congruence solving
Abstract— This paper addresses the problem of solving finite word-length (bit-vector) arithmetic with applications to equivalence verification of arithmetic datapaths. Arithmet...
Neal Tew, Priyank Kalla, Namrata Shekhar, Sivaram ...
ICCAD
2006
IEEE
108views Hardware» more  ICCAD 2006»
16 years 3 months ago
Formal model of data reuse analysis for hierarchical memory organizations
– In real-time data-dominated communication and multimedia processing applications, due to the manipulation of large sets of data, a multi-layer memory hierarchy is used to enhan...
Ilie I. Luican, Hongwei Zhu, Florin Balasa
ICCAD
2003
IEEE
123views Hardware» more  ICCAD 2003»
16 years 3 months ago
A Hybrid Approach to Nonlinear Macromodel Generation for Time-Varying Analog Circuits
Modeling frequency-dependent nonlinear characteristics of complex analog blocks and subsystems is critical for enabling efficient verification of mixed-signal system designs. Rece...
Peng Li, Xin Li, Yang Xu, Lawrence T. Pileggi
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