Sciweavers

1778 search results - page 93 / 356
» On the Power of the Randomized Iterate
Sort
View
ISVLSI
2008
IEEE
156views VLSI» more  ISVLSI 2008»
16 years 21 days ago
Cache Power Reduction in Presence of Within-Die Delay Variation Using Spare Ways
The share of leakage in cache power consumption increases with technology scaling. Choosing a higher threshold voltage (Vth) and/or gate-oxide thickness (Tox) for cache transistor...
Maziar Goudarzi, Tadayuki Matsumura, Tohru Ishihar...
ISVLSI
2003
IEEE
157views VLSI» more  ISVLSI 2003»
15 years 11 months ago
Joint Minimization of Power and Area in Scan Testing by Scan Cell Reordering
This paper describes a technique for re-ordering of scan cells to minimize power dissipation that is also capable of reducing the area overhead of the circuit compared to a random...
Shalini Ghosh, Sugato Basu, Nur A. Touba
DAC
1995
ACM
15 years 10 months ago
Register Allocation and Binding for Low Power
This paper describes a technique for calculating the switching activity of a set of registers shared by di erent data values. Based on the assumption that the joint pdf (probabili...
Jui-Ming Chang, Massoud Pedram
WINET
2002
124views more  WINET 2002»
15 years 6 months ago
CDMA Uplink Power Control as a Noncooperative Game
We present a game-theoretic treatment of distributed power control in CDMA wireless systems. We make use of the conceptual framework of noncooperative game theory to obtain a distr...
Tansu Alpcan, Tamer Basar, R. Srikant, Eitan Altma...
CEC
2005
IEEE
15 years 12 months ago
Dynamic power minimization during combinational circuit testing as a traveling salesman problem
Testing of VLSI circuits can cause generation of excessive heat which can damage the chips under test. In the random testing environment, high-performance CMOS circuits consume sig...
Artem Sokolov, Alodeep Sanyal, L. Darrell Whitley,...