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DAC
2001
ACM
16 years 7 months ago
Battery-Aware Static Scheduling for Distributed Real-Time Embedded Systems
This paper addresses battery-aware static scheduling in batterypowered distributed real-time embedded systems. As suggested by previous work, reducing the discharge current level ...
Jiong Luo, Niraj K. Jha
ISCAS
2008
IEEE
112views Hardware» more  ISCAS 2008»
16 years 17 days ago
Glitch-aware output switching activity from word-level statistics
— This paper presents models for estimating the transition activity of signals at the output of adders in Field Programmable Gate Arrays (FPGAs), given only word-level measures o...
Jonathan A. Clarke, George A. Constantinides, Pete...
DAC
2003
ACM
15 years 11 months ago
Low-power design methodology for an on-chip bus with adaptive bandwidth capability
This paper describes a low-power design methodology for a bus architecture based on hybrid current/voltage mode signaling for deep sub-micrometer on-chip interconnects that achiev...
Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III
ASPDAC
2004
ACM
75views Hardware» more  ASPDAC 2004»
15 years 11 months ago
Power-performance trade-off using pipeline delays
— We study the delays faced by instructions in the pipeline of a superscalar processor and its impact on power and performance. Instructions that are ready-on-dispatch (ROD) are ...
G. Surendra, Subhasis Banerjee, S. K. Nandy
VLSID
2002
IEEE
114views VLSI» more  VLSID 2002»
15 years 11 months ago
Minimizing Energy Consumption for High-Performance Processing
Power consumption is becoming an increasingly important constraint in the design of microprocessors. This paper examines the use of multiple constrained processors running at lowe...
Eric F. Weglarz, Kewal K. Saluja, Mikko H. Lipasti