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» On the Optimality of the Dimensionality Reduction Method
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ICCAD
2005
IEEE
168views Hardware» more  ICCAD 2005»
16 years 3 months ago
Statistical timing analysis driven post-silicon-tunable clock-tree synthesis
— Process variations cause significant timing uncertainty and yield degradation in deep sub-micron technologies. A solution to counter timing uncertainty is post-silicon clock t...
Jeng-Liang Tsai, Lizheng Zhang
ICMCS
2008
IEEE
175views Multimedia» more  ICMCS 2008»
16 years 15 days ago
Fast mode decision for adaptive prediction error coding
In [1], Adaptive Prediction Error Coding (APEC) in spatial and frequency domain is proposed and significantly improves the coding efficiency of video coders. However, this approac...
Cixun Zhang, Kemal Ugur, Moncef Gabbouj
GLVLSI
2007
IEEE
187views VLSI» more  GLVLSI 2007»
16 years 12 days ago
DAG based library-free technology mapping
This paper proposes a library-free technology mapping algorithm to reduce delay in combinational circuits. The algorithm reduces the overall number of series transistors through t...
Felipe S. Marques, Leomar S. da Rosa Jr., Renato P...
ESTIMEDIA
2007
Springer
16 years 7 days ago
Run-time Task Overlapping on Multiprocessor Platforms
Today’s embedded applications often consist of multiple concurrent tasks. These tasks are decomposed into subtasks which are in turn assigned and scheduled on multiple different...
Zhe Ma, Daniele Paolo Scarpazza, Francky Catthoor
LAWEB
2005
IEEE
15 years 11 months ago
A Latency-Based Object Placement Approach in Content Distribution Networks
Content Distribution Networks (CDNs) are increasingly being used to disseminate data in today's Internet aiming at reducing the load on the origin server and the traffic on t...
George Pallis, Athena Vakali, Konstantinos Stamos,...