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HPCA
2005
IEEE
16 years 6 months ago
Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture
This paper studies the impact of L2 cache sharing on threads that simultaneously share the cache, on a Chip Multi-Processor (CMP) architecture. Cache sharing impacts threads non-u...
Dhruba Chandra, Fei Guo, Seongbeom Kim, Yan Solihi...
HPCA
2002
IEEE
16 years 6 months ago
Evaluation of a Multithreaded Architecture for Cellular Computing
Cyclops is a new architecture for high performance parallel computers being developed at the IBM T. J. Watson Research Center. The basic cell of this architecture is a single-chip...
Calin Cascaval, José G. Castaños, Lu...
HPCA
2002
IEEE
16 years 6 months ago
Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay
Cache memories account for a significant fraction of a chip's overall energy dissipation. Recent research advocates using "resizable" caches to exploit cache requir...
Se-Hyun Yang, Michael D. Powell, Babak Falsafi, T....
HPCA
2001
IEEE
16 years 6 months ago
CARS: A New Code Generation Framework for Clustered ILP Processors
Clustered ILP processors are characterized by a large number of non-centralized on-chip resources grouped into clusters. Traditional code generation schemes for these processors c...
Krishnan Kailas, Kemal Ebcioglu, Ashok K. Agrawala
STOC
2006
ACM
174views Algorithms» more  STOC 2006»
16 years 6 months ago
Edge-disjoint paths in Planar graphs with constant congestion
We study the maximum edge-disjoint paths problem in undirected planar graphs: given a graph G and node pairs s1t1, s2t2, . . ., sktk, the goal is to maximize the number of pairs t...
Chandra Chekuri, Sanjeev Khanna, F. Bruce Shepherd
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