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IPPS
2006
IEEE
16 years 18 days ago
Analysis of checksum-based execution schemes for pipelined processors
The performance requirements for contemporary microprocessors are increasing as rapidly as their number of applications grows. By accelerating the clock, performance can be gained...
Bernhard Fechner
IPPS
2006
IEEE
16 years 18 days ago
SAMIE-LSQ: set-associative multiple-instruction entry load/store queue
The load/store queue (LSQ) is one of the most complex parts of contemporary processors. Its latency is critical for the processor performance and it is usually one of the processo...
Jaume Abella, Antonio González
IPPS
2006
IEEE
16 years 18 days ago
A study of the on-chip interconnection network for the IBM Cyclops64 multi-core architecture
The designs of high-performance processor architectures are moving toward the integration of a large number of multiple processing cores on a single chip. The IBM Cyclops-64 (C64)...
Yingping Zhang, Taikyeong Jeong, Fei Chen, Haiping...
IPPS
2006
IEEE
16 years 18 days ago
Broadcasting and routing in faulty mesh networks
— Broadcasting is a data communication task in which one processor sends the same message to all other processors. Routing is a task where a source processor sends a message to a...
Milos Stojmenovic, Amiya Nayak
IPPS
2006
IEEE
16 years 18 days ago
A case for exploit-robust and attack-aware protocol RFCs
A large number of vulnerabilities occur because protocol implementations failed to anticipate illegal packets. rfcs typically define what constitute “right” packets relevant ...
Venkat Pothamsetty, Prabhaker Mateti
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