Sciweavers

8086 search results - page 379 / 1618
» On the Implementation of Dynamic Patterns
Sort
View
ICFP
2007
ACM
16 years 6 months ago
Functional pearl: the great escape or, how to jump the border without getting caught
Filinski showed that callcc and a single mutable reference cell are sufficient to express the delimited control operators shift and reset. However, this implementation interacts p...
David Herman
EPIA
2005
Springer
16 years 11 days ago
Operational Semantics for DyLPs
Theoretical research has spent some years facing the problem of how to represent and provide semantics to updates of logic programs. This problem is relevant for addressing highly ...
Federico Banti, José Júlio Alferes, ...
GLVLSI
2003
IEEE
195views VLSI» more  GLVLSI 2003»
16 years 4 days ago
A pipelined clock-delayed domino carry-lookahead adder
Clock-delayed (CD) domino is a dynamic logic family developed to provide both inverting and non-inverting logic on single-rail gates. It is self-timed and can be easily pipelined ...
Bhushan A. Shinkre, James E. Stine
152
Voted
IPPS
2003
IEEE
16 years 4 days ago
Sequence Alignment on the Cray MTA-2
The standard algorithm for alignment of DNA sequences using dynamic programming has been implemented on the Cray MTA-2 (Multithreaded Architecture-2) at ENRI (Electronic Navigatio...
Shahid H. Bokhari, Jon R. Sauer
FPL
2008
Springer
104views Hardware» more  FPL 2008»
15 years 8 months ago
A technique for minimizing power during FPGA placement
This paper considers the implementation of an annealing technique for dynamic power reduction in FPGAs. The proposed method comprises a power-aware objective function for placemen...
Kristofer Vorwerk, Madhu Raman, Julien Dunoyer, Ya...