Abstract-This paper proposes the use of four-transistor (4T) cache and branch predictor array cell designs to address increasing worries regarding leakage power dissipation. While ...
Philo Juang, Phil Diodato, Stefanos Kaxiras, Kevin...
Transactional memory is a promising, optimistic synchronization mechanism for chip-multiprocessor systems. The simplicity of atomic sections, instead of using explicit locks, is al...
Verifying concurrent programs is challenging since the number of thread interleavings that need to be explored can be huge even for moderate programs. We present a cartesian semant...
Guy Gueta, Cormac Flanagan, Eran Yahav, Mooly Sagi...
The ability to simulate a seaport environment, including illicit cargo and the sensors designed to detect such cargo, allows the evaluation of alternative detection methods in orde...
Allen Christiansen, Damian Johnson, Lawrence B. Ho...
Since the end of 2004, when the law decree about accessibility for Brazilian governmental websites came into force, the federal agencies have been struggling to conform to the nor...