In this paper, we study the interconnect layout optimization problem under a higher-order RLC model to optimize not just delay, but also waveform for RLC circuits with non-monoton...
Functional simulation is the most widely used method for design verification. At various levels of abstraction, e.g., behavioral, register-transfer level and gate level, the design...
Abstract. In this paper a rigorous mathematical framework of deterministic annealing and mean-field approximation is presented for a general class of partitioning, clustering and ...
In this paper we describe our experiments on a realtime system design, focusing on design alternatives such as scheduling jitter, sensor-to-output latency, intertask communication...
Namyun Kim, Minsoo Ryu, Seongsoo Hong, Manas Sakse...
This paper discusses a Genetic Algorithm-based method of generating test vectorsfor detecting faults in combinational circuits. The GA-based approach combines the merits of two te...