5891 search results - page 874 / 1179 » On the Computational Security of a Distributed Key Distribut... |
150
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HPCA
2008
IEEE
16 years 7 months ago
2008
IEEE
The interconnect mechanisms (shared bus or crossbar) used in current chip-multiprocessors (CMPs) are expected to become a bottleneck that prevents these architectures from scaling...
161
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HPCA
2006
IEEE
16 years 7 months ago
2006
IEEE
Transactional memory (TM) provides an easy-to-use and high-performance parallel programming model for the upcoming chip-multiprocessor systems. Several researchers have proposed a...
150
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HPCA
2003
IEEE
16 years 7 months ago
2003
IEEE
Thread-level speculation provides architectural support to aggressively run hard-to-analyze code in parallel. As speculative tasks run concurrently, they generate unsafe or specul...
191
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RECOMB
2003
Springer
16 years 7 months ago
2003
Springer
We propose a framework for modeling sequence motifs based on the maximum entropy principle (MEP). We recommend approximating short sequence motif distributions with the maximum en...
225
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OSDI
2004
ACM
16 years 7 months ago
2004
ACM
MapReduce is a programming model and an associated implementation for processing and generating large data sets. Users specify a map function that processes a key/value pair to ge...