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VLSID
2004
IEEE
146views VLSI» more  VLSID 2004»
16 years 7 months ago
CMOS Circuit Design for Minimum Dynamic Power and Highest Speed
{A new low-power design method produces CMOS circuits that consume the least dynamic power at the highest speed permitted under the technology constraint. A gate is characterized b...
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...
VLSID
2002
IEEE
207views VLSI» more  VLSID 2002»
16 years 7 months ago
Synthesis of High Performance Low Power Dynamic CMOS Circuits
This paper presents a novel approach for the synthesis of dynamic CMOS circuits using Domino and Nora styles. As these logic styles can implement only non-inverting logic, convent...
Debasis Samanta, Nishant Sinha, Ajit Pal
INFOCOM
2006
IEEE
16 years 20 days ago
Distributed Uplink Power Control for Optimal SIR Assignment in Cellular Data Networks
Abstract—This paper solves the joint power control and SIR assignment problem through distributed algorithms in the uplink of multi-cellular wireless networks. The 1993 Foschini-...
Prashanth Hande, Sundeep Rangan, Mung Chiang
ISLPED
2005
ACM
109views Hardware» more  ISLPED 2005»
16 years 6 days ago
Power reduction by varying sampling rate
The rate at which a digital signal processing (DSP) system operates depends on the highest frequency component in the input signal. DSP applications must sample their inputs at a ...
William R. Dieter, Srabosti Datta, Wong Key Kai
MOBIHOC
2004
ACM
16 years 6 months ago
A single-channel solution for transmission power control in wireless ad hoc networks
Transmission power control (TPC) has a great potential to increase the throughput of a mobile ad hoc network (MANET). Existing TPC schemes achieve this goal by using additional ha...
Alaa Muqattash, Marwan Krunz