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ISLPED
1995
ACM
193views Hardware» more  ISLPED 1995»
15 years 10 months ago
Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint
We consider the problem of transistor sizing in a static CMOS layout to minimizethe power consumption of the circuit subject to a given delay constraint. Based on our characteriza...
Manjit Borah, Robert Michael Owens, Mary Jane Irwi...
JEC
2006
71views more  JEC 2006»
15 years 6 months ago
Destructive-read in embedded DRAM, impact on power consumption
This paper explores power consumption for destructive-read embedded DRAM. Destructive-read DRAM is based on conventional DRAM design, but with sense amplifiers optimized for lower ...
Haakon Dybdahl, Per Gunnar Kjeldsberg, Marius Gran...
KES
2006
Springer
15 years 6 months ago
Intelligent Environment for Training of Power Systems Operators
Training of operators has become an important problem to be faced by power systems: updating knowledge and skills. An operator must comprehend the physical operation of the process...
Gustavo Arroyo-Figueroa, Yasmín Herná...
CE
2005
58views more  CE 2005»
15 years 6 months ago
Does ICT contribute to powerful learning environments in primary education?
In powerful learning environments, rich contexts and authentic tasks are presented to pupils. Active, autonomous and co-operative learning is stimulated, and the curriculum is ada...
Ed Smeets
ISITA
2010
15 years 3 months ago
Performance analysis and optimal power allocation for hybrid incremental relaying
Relaying technique has been developed considerable attention in response to improve reliability and to extend wireless network coverage. One of conventional relaying technique, inc...
Jaeyoung Lee, Sung-il Kim, Jun Heo