7200 search results - page 221 / 1440 » On the Computational Power of Winner-Take-All |
202
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HOTI
2011
IEEE
14 years 6 months ago
2011
IEEE
Abstract—Network-on-Chips (NoCs) paradigm is fast becoming a defacto standard for designing communication infrastructure for multicores with the dual goals of reducing power cons...
191
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ASPLOS
2012
ACM
14 years 2 months ago
2012
ACM
Numerous data center services exhibit low average utilization leading to poor energy efficiency. Although CPU voltage and frequency scaling historically has been an effective mea...
197
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HPCA
2012
IEEE
14 years 2 months ago
2012
IEEE
Lowering supply voltage is one of the most effective techniques for reducing microprocessor power consumption. Unfortunately, at low voltages, chips are very sensitive to process ...
151
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DAC
2008
ACM
16 years 7 months ago
2008
ACM
Technological advances enable modern processors to utilize increasingly larger DRAMs with rising access frequencies. This is leading to high power consumption and operating temper...
165
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DAC
2003
ACM
16 years 7 months ago
2003
ACM
With the scaling of technology, power grid noise is becoming increasingly significant for circuit performance. A typical power grid circuit contains millions of linear elements, m...