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TPDS
2010
98views more  TPDS 2010»
15 years 4 months ago
The Synchronization Power of Coalesced Memory Accesses
—Multicore architectures have established themselves as the new generation of computer architectures. As part of the one core to many cores evolution, memory access mechanisms ha...
Phuong Hoai Ha, Philippas Tsigas, Otto J. Anshus
LATIN
2004
Springer
15 years 12 months ago
Approximating the Expressive Power of Logics in Finite Models
Abstract. We present a probability logic (essentially a first order language extended with quantifiers that count the fraction of elements in a model that satisfy a first order ...
Argimiro Arratia, Carlos E. Ortiz
MICRO
2003
IEEE
166views Hardware» more  MICRO 2003»
15 years 12 months ago
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pa...
HPCA
1999
IEEE
15 years 11 months ago
Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance
In general-purpose microprocessors, recent trends have pushed towards 64-bit word widths, primarily to accommodate the large addressing needs of some programs. Many integer proble...
David Brooks, Margaret Martonosi
ICCAD
2009
IEEE
179views Hardware» more  ICCAD 2009»
15 years 4 months ago
Automatic memory partitioning and scheduling for throughput and power optimization
Hardware acceleration is crucial in modern embedded system design to meet the explosive demands on performance and cost. Selected computation kernels for acceleration are usually ...
Jason Cong, Wei Jiang, Bin Liu, Yi Zou