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ASPDAC
2004
ACM
141views Hardware» more  ASPDAC 2004»
15 years 12 months ago
An approach for reducing dynamic power consumption in synchronous sequential digital designs
— The problem of minimizing dynamic power consumption by scaling down the supply voltage of computational elements off critical paths is widely addressed in the literature for th...
Noureddine Chabini, Wayne Wolf
DAC
1999
ACM
15 years 10 months ago
Synthesis of Low Power CMOS VLSI Circuits Using Dual Supply Voltages
Dynamic power consumed in CMOS gates goes down quadratically with the supply voltage. By maintaining a high supply voltage for gates on the critical path and by using a low supply...
Vijay Sundararajan, Keshab K. Parhi
WCNC
2010
IEEE
15 years 10 months ago
Joint Optimization of Power Allocation and Relay Deployment in Wireless Sensor Networks
—We study the problem of optimizing the symbol error probability (SEP) performance of cluster-based cooperative wireless sensor networks (WSNs). It is shown in the literature tha...
Mohammad Abdizadeh, Hadi Jamali Rad, Bahman Abolha...
ICASSP
2010
IEEE
15 years 6 months ago
Power law discounting for n-gram language models
We present an approximation to the Bayesian hierarchical PitmanYor process language model which maintains the power law distribution over word tokens, while not requiring a comput...
Songfang Huang, Steve Renals
TC
2002
15 years 6 months ago
Dynamic Power Management for Nonstationary Service Requests
Dynamic Power Management (DPM) is a design methodology aiming at reducing power consumption of electronic systems by performing selective shutdown of idle system resources. The eff...
Eui-Young Chung, Luca Benini, Alessandro Bogliolo,...