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HPCA
2003
IEEE
16 years 6 months ago
Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks
Originally developed to connect processors and memories in multicomputers, prior research and design of interconnection networks have focused largely on performance. As these netw...
Li Shang, Li-Shiuan Peh, Niraj K. Jha
ISLPED
2006
ACM
74views Hardware» more  ISLPED 2006»
16 years 10 days ago
Power phase variation in a commercial server workload
Many techniques have been developed for adaptive power management of computing systems. These techniques rely on the presence of varying power phases to detect opportunities for a...
W. L. Bircher, L. K. John
HPCA
2005
IEEE
16 years 9 hour ago
Exploring the Design Space of Power-Aware Opto-Electronic Networked Systems
As microprocessors become increasingly interconnected, the power consumed by the interconnection network can no longer be ignored. Moreover, with demand for link bandwidth increas...
Xuning Chen, Li-Shiuan Peh, Gu-Yeon Wei, Yue-Kai H...
DAC
2005
ACM
15 years 8 months ago
Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages
Minimizing power consumption is one of the most important objectives in IC design. Resizing gates and assigning different Vt’s are common ways to meet power and timing budgets. ...
Feng Gao, John P. Hayes
HPCA
2008
IEEE
16 years 6 months ago
Power-Efficient DRAM Speculation
Power-Efficient DRAM Speculation (PEDS) is a power optimization targeted at broadcast-based sharedmemory multiprocessor systems that speculatively access DRAM in parallel with the...
Nidhi Aggarwal, Jason F. Cantin, Mikko H. Lipasti,...