7200 search results - page 139 / 1440 » On the Computational Power of Winner-Take-All |
129
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VLSID
2002
IEEE
16 years 6 months ago
2002
IEEE
As a basic cell of arithmetic circuits, a one-bit full adder and a counter are usually used. Minimizing power consumption of these components is a key issue for low-power circuit ...
130
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LCN
2003
IEEE
15 years 11 months ago
2003
IEEE
We evaluate the performance of IP paging with power save mechanism by formulating an analytical model and carrying out simulation study of Integrated IP Paging Protocol (IIPP) tha...
167
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OSDI
2008
ACM
16 years 6 months ago
2008
ACM
: ? Delivering Energy Proportionality with Non Energy-Proportional Systems-Optimizing the Ensemble Niraj Tolia, Zhikui Wang, Manish Marwah, Cullen Bash, Parthasarathy Ranganathan, ...
171
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GLVLSI
2007
IEEE
15 years 8 months ago
2007
IEEE
We present a vector selection methodology for estimating the peak power dissipation in a CMOS logic circuit. The ultimate goal is to combine the speed of RT-level simulation with ...
145
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VLSID
2002
IEEE
16 years 6 months ago
2002
IEEE
In this paper, we address the problem of power dissipation minimization in combinational circuits implemented using pass transistor logic (PTL). We transform the problem of power ...