Sciweavers

129 search results - page 24 / 26
» On the Computational Power of Threshold Circuits with Sparse...
Sort
View
CORR
2011
Springer
198views Education» more  CORR 2011»
15 years 29 days ago
Kron Reduction of Graphs with Applications to Electrical Networks
Abstract. Consider a weighted and undirected graph, possibly with self-loops, and its corresponding Laplacian matrix, possibly augmented with additional diagonal elements correspon...
Florian Dörfler, Francesco Bullo
ISLPED
2007
ACM
169views Hardware» more  ISLPED 2007»
15 years 7 months ago
Throughput of multi-core processors under thermal constraints
We analyze the effect of thermal constraints on the performance and power of multi-core processors. We propose system-level power and thermal models, and derive expressions for (a...
Ravishankar Rao, Sarma B. K. Vrudhula, Chaitali Ch...
GLVLSI
2007
IEEE
189views VLSI» more  GLVLSI 2007»
16 years 9 days ago
Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems
The path-delay fault simulation of functional tests on complex circuits such as current processor-based systems is a daunting task. The amount of computing power and memory needed...
Paolo Bernardi, Michelangelo Grosso, Matteo Sonza ...
ISLPED
2007
ACM
96views Hardware» more  ISLPED 2007»
15 years 7 months ago
Low-power process-variation tolerant arithmetic units using input-based elastic clocking
In this paper we propose a design methodology for low-power, high-performance, process-variation tolerant architecture for arithmetic units. The novelty of our approach lies in th...
Debabrata Mohapatra, Georgios Karakonstantis, Kaus...
ISCAS
2006
IEEE
162views Hardware» more  ISCAS 2006»
15 years 12 months ago
Silicon neurons that phase-lock
Abstract—We present a silicon neuron with a dynamic, active leak that enables precise spike-timing with respect to a time-varying input signal. Our neuron models the mammalian bu...
J. H. Wittig Jr., Kwabena Boahen