In this paper we present an optimization solution for power and performance management in a platform running multiple independent applications. Our approach assumes a virtualized ...
Vinicius Petrucci, Orlando Loques, Daniel Moss&eac...
In this paper, we describe a technique for power reduction in sequential circuits. Existing signals in the circuit are used to selectively disable some of the registers so that a ...
—In this work the design of a low power 10-bit 100MS/s pipeline ADC is presented. Low power consumption is realized by using an optimum bit per stage resolution and also by apply...
We present a system-level approach for power optimization under a set of user specified costs and timing constraints of hard real-time designs. The approach optimizes all three d...
In this paper we consider MIMO system with Mt transmitting and Mr receiving antennas, when channel state information (CSI) is known on the transmitter side. The Reyleigh fading cha...