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ISPD
2010
ACM
160views Hardware» more  ISPD 2010»
16 years 1 months ago
Physical synthesis of bus matrix for high bandwidth low power on-chip communications
As the thermal wall becomes the dominant factor limiting VLSI circuit performance, and the interconnect wires become the primary power consumer, power efficiency of onchip data th...
Renshen Wang, Evangeline F. Y. Young, Ronald L. Gr...
VLSID
2008
IEEE
142views VLSI» more  VLSID 2008»
16 years 28 days ago
Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures
With the shift towards deep sub-micron (DSM) technologies, the increase in leakage power and the adoption of poweraware design methodologies have resulted in potentially significa...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
ICC
2007
IEEE
16 years 27 days ago
Power Managed Packet Switching
— High power dissipation in packet switches and routers is fast turning into a key problem, owing to increasing line speeds and decreasing chip sizes. To address this issue, we i...
Aditya Dua, Benjamin Yolken, Nicholas Bambos
ICCS
2007
Springer
16 years 21 days ago
Implementing Virtual Buffer for Electric Power Grids
The electric power grid is a vital network for every aspect of our life. The lack of buffer between generation and consumption makes the power grid unstable and fragile. While larg...
Rong Gao, Lefteri H. Tsoukalas
IJCNN
2006
IEEE
16 years 18 days ago
Particle Swarm Optimization based Defensive Islanding of Large Scale Power System
— Defensive islanding is an efficient way to avoid catastrophic failures and wide area blackouts. Power system splitting especially for large scale power systems is a combinatori...
Wenxin Liu, David A. Cartes, Ganesh K. Venayagamoo...