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BROADNETS
2007
IEEE
16 years 22 days ago
Reconsidering power management
— Power-management approaches have been widely studied in an attempt to conserve idling energy by allowing nodes to switch to a low-power sleep mode. However, due to the inherent...
Cigdem Sengul, Albert F. Harris III, Robin Kravets
CCECE
2006
IEEE
16 years 14 days ago
A High-Speed Low-Power Rail-to-Rail Buffer Amplifier for LCD Application
A high-speed low-power rail-to-rail class-B buffer amplifier, which is suitable for liquid crystal display applications, is proposed. The summing circuit is biased by the constant...
Chih-Wen Lu, Peter H. Xiao
IPPS
2005
IEEE
15 years 12 months ago
Toward an Evaluation Infrastructure for Power and Energy Optimizations
Execution-driven simulators are often used for power/energy and performance evaluation. Simulators can provide semantic details but they provide insufficient speed and accuracy f...
Chunling Hu, Daniel A. Jiménez, Ulrich Krem...
ASPDAC
2004
ACM
141views Hardware» more  ASPDAC 2004»
15 years 11 months ago
An approach for reducing dynamic power consumption in synchronous sequential digital designs
— The problem of minimizing dynamic power consumption by scaling down the supply voltage of computational elements off critical paths is widely addressed in the literature for th...
Noureddine Chabini, Wayne Wolf
DAC
1999
ACM
15 years 10 months ago
Synthesis of Low Power CMOS VLSI Circuits Using Dual Supply Voltages
Dynamic power consumed in CMOS gates goes down quadratically with the supply voltage. By maintaining a high supply voltage for gates on the critical path and by using a low supply...
Vijay Sundararajan, Keshab K. Parhi