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DAC
2005
ACM
15 years 8 months ago
Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages
Minimizing power consumption is one of the most important objectives in IC design. Resizing gates and assigning different Vt’s are common ways to meet power and timing budgets. ...
Feng Gao, John P. Hayes
HPCA
2008
IEEE
16 years 6 months ago
Power-Efficient DRAM Speculation
Power-Efficient DRAM Speculation (PEDS) is a power optimization targeted at broadcast-based sharedmemory multiprocessor systems that speculatively access DRAM in parallel with the...
Nidhi Aggarwal, Jason F. Cantin, Mikko H. Lipasti,...
HPCA
2005
IEEE
16 years 6 months ago
On the Limits of Leakage Power Reduction in Caches
If current technology scaling trends hold, leakage power dissipation will soon become the dominant source of power consumption in high performance processors. Caches, due to the f...
Yan Meng, Timothy Sherwood, Ryan Kastner
ICDE
2010
IEEE
292views Database» more  ICDE 2010»
16 years 6 months ago
Exploring Power-Performance Tradeoffs in Database Systems
With the total energy consumption of computing systems increasing in a steep rate, much attention has been paid to the design of energy-efficient computing systems and applications...
Zichen Xu, Yi-Cheng Tu, Xiaorui Wang
APSCC
2008
IEEE
16 years 26 days ago
Algorithms for Transmission Power Control in Biomedical Wireless Sensor Networks
—Wireless sensor networks are increasingly being used for continuous monitoring of patients with chronic health conditions such as diabetes and heart problems. As biomedical sens...
Ashay Dhamdhere, Vijay Sivaraman, Vidit Mathur, Sh...