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GLVLSI
2007
IEEE
158views VLSI» more  GLVLSI 2007»
15 years 8 months ago
RT-level vector selection for realistic peak power simulation
We present a vector selection methodology for estimating the peak power dissipation in a CMOS logic circuit. The ultimate goal is to combine the speed of RT-level simulation with ...
Chia-Chien Weng, Ching-Shang Yang, Shi-Yu Huang
VLSID
2002
IEEE
135views VLSI» more  VLSID 2002»
16 years 6 months ago
An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis
In this paper, we address the problem of power dissipation minimization in combinational circuits implemented using pass transistor logic (PTL). We transform the problem of power ...
Rupesh S. Shelar, Sachin S. Sapatnekar
EWSN
2006
Springer
16 years 6 months ago
Power Management for Bluetooth Sensor Networks
Low power is a primary concern in the field of wireless sensor networks. Bluetooth has often been labeled as an inappropriate technology in this field due to its high power consump...
Luca Negri, Lothar Thiele
FORMATS
2009
Springer
16 years 28 days ago
Exploiting Timed Automata for Conformance Testing of Power Measurements
For software development, testing is still the primary choice for investigating the correctness of a system. Automated testing is of utmost importance to support continuous integra...
Matthias Woehrle, Kai Lampka, Lothar Thiele
DATE
2006
IEEE
176views Hardware» more  DATE 2006»
16 years 13 days ago
Low power synthesis of dynamic logic circuits using fine-grained clock gating
— Clock power consumes a significant fraction of total power dissipation in high speed precharge/evaluate logic styles. In this paper, we present a novel low-cost design methodol...
Nilanjan Banerjee, Kaushik Roy, Hamid Mahmoodi-Mei...