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ICCAD
2007
IEEE
125views Hardware» more  ICCAD 2007»
16 years 3 months ago
A methodology for timing model characterization for statistical static timing analysis
While the increasing need for addressing process variability in sub-90nm VLSI technologies has sparkled a large body of statistical timing and optimization research, the realizati...
Zhuo Feng, Peng Li
ICCAD
2004
IEEE
125views Hardware» more  ICCAD 2004»
16 years 3 months ago
Temporal floorplanning using the T-tree formulation
Improving logic capacity by time-sharing, dynamically reconfigurable FPGAs are employed to handle designs of high complexity and functionality. In this paper, we model each task ...
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
182
Voted
ICCAD
2001
IEEE
111views Hardware» more  ICCAD 2001»
16 years 3 months ago
Congestion Aware Layout Driven Logic Synthesis
In this paper, we present novel algorithms that effectively combine physical layout and early logic synthesis to improve overall design quality. In addition, we employ partitionin...
Thomas Kutzschebauch, Leon Stok
TLDI
2010
ACM
218views Formal Methods» more  TLDI 2010»
16 years 3 months ago
Pointwise generalized algebraic data types
In the GADT (Generalized Algebraic Data Types) type system, a pattern-matching branch can draw type information from both the scrutinee type and the data constructor type. Even th...
Chuan-kai Lin, Tim Sheard
172
Voted
PEPM
2010
ACM
16 years 3 months ago
Clone detection and elimination for Haskell
Duplicated code is a well known problem in software maintenance and refactoring. Code clones tend to increase program size and several studies have shown that duplicated code make...
Christopher Brown, Simon Thompson
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