Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
A major challenge in the design of wireless networks is the need for distributed scheduling algorithms that will efficiently share the common spectrum. Recently, a few distributed...
We study an economic setting in which a principal motivates a team of strategic agents to exert costly effort toward the success of a joint project. The action taken by each agent...
Abstract—We analyze the performance limits of data dissemination with multi-channel, single radio sensors. We formulate the problem of minimizing the average delay of data dissem...
David Starobinski, Weiyao Xiao, Xiangping Qin, Ari...
Historically, compilers have operated by applying a fixed set of optimizations in a predetermined order. We call such an ordered list of optimizations a compilation sequence. This...
Keith D. Cooper, Devika Subramanian, Linda Torczon