We give an overview of the enhanced VSE system which is a tool to formally specify and verify systems. It provides means for structuring speci cations and it supports the developme...
Dieter Hutter, Heiko Mantel, Georg Rock, Werner St...
Abstract. We study entailment of structural and nonstructural recursive subtyping constraints. Constraints are formal inequalities between type expressions, interpreted over an ord...
This paper proposes extensions to the VHDL grammar and denes new semantics in the language to model the timing behavior of high frequency buses and clock lines with multiple, dis...