This paper presents an efficient modeling scheme and a partitioning heuristic for parallelizing VLSI post-placement timing optimization. Encoding the paths with timing violations...
Abstract. The development of veracious models of the Internet topology has received a lot of attention in the last few years. Many proposed models are based on topologies derived f...
Xenofontas A. Dimitropoulos, Dmitri V. Krioukov, G...
This paper describes a new design methodology to analyze the on-chip power supply noise for high performance microprocessors. Based on an integrated package-level and chip-level p...
In this paper, we extend the classical result by Huang, Kintala, Kolettis and Fulton (1995), and in addition propose a modified stochastic model to determine the software rejuvena...
In this paper, we address the task of mapping high-level instructions to sequences of commands in an external environment. Processing these instructions is challenging--they posit...
S. R. K. Branavan, Luke S. Zettlemoyer, Regina Bar...