10718 search results - page 746 / 2144 » On the Circuit Implementation Problem |
208
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DATE
2006
IEEE
16 years 1 months ago
2006
IEEE
—The clock distribution network is a key component of any synchronous VLSI design. High power dissipation and pressure volume temperature-induced variations in clock skew have st...
208
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ETS
2006
IEEE
16 years 1 months ago
2006
IEEE
- The resources available on a chip continue to grow, following Moore's Law. However, the major process by which the benefits of Moore's Law accrue, which is the continui...
181
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VTS
2006
IEEE
16 years 1 months ago
2006
IEEE
We tackle the problem of fault-free assumptions in current PLB and interconnect built-in-self-test (BIST) techniques for FPGAs. These assumptions were made in order to develop stro...
226
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CASES
2006
ACM
16 years 1 months ago
2006
ACM
Designers of SoCs with non-digital components, such as analog or MEMS devices, can currently use high-level system design languages, such as SystemC, to model only the digital par...
209
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ISPD
2006
ACM
16 years 1 months ago
2006
ACM
Linear programming (LP) based methods are attractive for solving the placement problem because of their ability to model Half-Perimeter Wirelength (HPWL) and timing. However, it h...