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ITC
2002
IEEE
114views Hardware» more  ITC 2002»
16 years 5 days ago
Scan Power Reduction Through Test Data Transition Frequency Analysis
Significant reductions in test application times can be achieved through parallelizing core tests; however, simultaneous test of various cores may result in exceeding power thres...
Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailog...
VLSID
2002
IEEE
192views VLSI» more  VLSID 2002»
16 years 4 days ago
Static and Dynamic Variable Voltage Scheduling Algorithms for Real-Time Heterogeneous Distributed Embedded Systems
à This paper addresses the problem of static and dynamic variable voltage scheduling of multi-rate periodic task graphs (i.e., tasks with precedence relationships) and aperiodic t...
Jiong Luo, Niraj K. Jha
SIGECOM
2010
ACM
184views ECommerce» more  SIGECOM 2010»
16 years 2 days ago
Computing pure strategy nash equilibria in compact symmetric games
We analyze the complexity of computing pure strategy Nash equilibria (PSNE) in symmetric games with a fixed number of actions. We restrict ourselves to “compact” representati...
Christopher Thomas Ryan, Albert Xin Jiang, Kevin L...
VTS
2000
IEEE
94views Hardware» more  VTS 2000»
15 years 11 months ago
On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set
1 This paper addresses the problem of testing path delay faults in a microprocessor using instructions. It is observed that a structurally testable path (i.e., a path testable thro...
Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng
ASPDAC
2000
ACM
159views Hardware» more  ASPDAC 2000»
15 years 11 months ago
Analytical minimization of half-perimeter wirelength
Global placement of hypergraphs is critical in the top-down placement of large timing-driven designs 10, 16 . Placement quality is evaluated in terms of the half-perimeter wirelen...
Andrew A. Kennings, Igor L. Markov