10718 search results - page 575 / 2144 » On the Circuit Implementation Problem |
226
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ISPD
2009
ACM
16 years 2 months ago
2009
ACM
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignmen...
192
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MOBICOM
2009
ACM
16 years 1 months ago
2009
ACM
This paper presents the design challenges posed by a new class of ultra-low-power devices referred to as Energy-Harvesting Active Networked Tags (EnHANTs). EnHANTs are small, fle...
207
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GLVLSI
2006
IEEE
16 years 1 months ago
2006
IEEE
Process technology and environment-induced variability of gates and wires in VLSI circuits make timing analyses of such circuits a challenging task. Process variation can have a s...
186
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ISCAS
2006
IEEE
16 years 1 months ago
2006
IEEE
Abstract—We present a silicon neuron with a dynamic, active leak that enables precise spike-timing with respect to a time-varying input signal. Our neuron models the mammalian bu...
170
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ASPDAC
2006
ACM
16 years 1 months ago
2006
ACM
— Due to its great flexibility, gridless routing is desirable for nanometer circuit designs that use variable wire widths and spacings. Nevertheless, it is much more difficult ...