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» On the Circuit Implementation Problem
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IJCSA
2008
100views more  IJCSA 2008»
15 years 7 months ago
A Smart Architecture for Low-Level Image Computing
This paper presents a comparison relating two different vision system architectures. The first one involves a smart sensor including analog processors allowing on-chip image proce...
A. Elouardi, Samir Bouaziz, Antoine Dupret, Lionel...
IJON
2006
56views more  IJON 2006»
15 years 7 months ago
A computational model of anterior intraparietal (AIP) neurons
The monkey parietal anterior intraparietal area (AIP) is part of the grasp planning and execution circuit which contains neurons that encode object features relevant for grasping,...
Erhan Oztop, Hiroshi Imamizu, Gordon Cheng, Mitsuo...
IJON
2006
189views more  IJON 2006»
15 years 7 months ago
Storing and restoring visual input with collaborative rank coding and associative memory
Associative memory in cortical circuits has been held as a major mechanism for content-addressable memory. Hebbian synapses implement associative memory efficiently when storing s...
Martin Rehn, Friedrich T. Sommer
JSA
2006
113views more  JSA 2006»
15 years 7 months ago
A power-efficient TCAM architecture for network forwarding tables
Stringent memory access and search speed requirements are two of the main bottlenecks in wire speed processing. Most viable search engines are implemented in content addressable m...
Taskin Koçak, Faysal Basci
IJCSS
2007
133views more  IJCSS 2007»
15 years 7 months ago
Synthesis of Read-Once Digital Hardware with Reduced Energy Delay Product
This paper presents a low power driven synthesis framework for the unique class of nonregenerative Boolean Read-Once Functions (BROF). A two-pronged approach is adopted, where the...
P. Balasubramanian, S. Theja