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» On the Circuit Implementation Problem
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FPL
2009
Springer
96views Hardware» more  FPL 2009»
15 years 11 months ago
Noise impact of single-event upsets on an FPGA-based digital filter
Field-programmable gate arrays are well-suited to DSP and digital communications applications. SRAM-based FPGAs, however, are susceptible to radiation-induced single-event upsets ...
Brian H. Pratt, Michael J. Wirthlin, Michael P. Ca...
FPGA
2001
ACM
152views FPGA» more  FPGA 2001»
15 years 11 months ago
A pipelined architecture for partitioned DWT based lossy image compression using FPGA's
Discrete wavelet transformations (DWT) followed by embedded zerotree encoding is a very efficient technique for image compression [2, 5, 4]. However, the algorithms proposed in l...
Jörg Ritter, Paul Molitor
HYBRID
2001
Springer
15 years 11 months ago
Hybrid Modeling and Simulation of Biomolecular Networks
Abstract. In a biological cell, cellular functions and the genetic regulatory apparatus are implemented and controlled by a network of chemical reactions in which regulatory protei...
Rajeev Alur, Calin Belta, Franjo Ivancic
ITC
2000
IEEE
101views Hardware» more  ITC 2000»
15 years 11 months ago
Which concurrent error detection scheme to choose ?
Concurrent error detection (CED) techniques (based on hardware duplication, parity codes, etc.) are widely used to enhance system dependability. All CED techniques introduce some ...
Subhasish Mitra, Edward J. McCluskey
ASPDAC
2000
ACM
111views Hardware» more  ASPDAC 2000»
15 years 11 months ago
Gate-level aged timing simulation methodology for hot-carrier reliability assurance
- This paper presents a new aged timing simulation methodology that can be used for hot-carrier reliability assurance of VLSI. This methodology consists of a compact model and a un...
Yoshiyuki Kawakami, Jingkun Fang, Hirokazu Yonezaw...