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ISCA
2002
IEEE
112views Hardware» more  ISCA 2002»
16 years 3 days ago
Drowsy Caches: Simple Techniques for Reducing Leakage Power
On-chip caches represent a sizable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potential...
Krisztián Flautner, Nam Sung Kim, Steven M....
ISCAS
2002
IEEE
125views Hardware» more  ISCAS 2002»
16 years 3 days ago
Switching activity estimation of finite state machines for low power synthesis
A technique for computing the switching activity of synchronous Finite State Machine (FSM) implementations including the influence of temporal correlation among the next state si...
Mikael Kerttu, Per Lindgren, Mitchell A. Thornton,...
VLSID
2002
IEEE
100views VLSI» more  VLSID 2002»
16 years 2 days ago
Layout-Driven Timing Optimization by Generalized De Morgan Transform
We propose a timing-oriented logic optimization technique called Generalized De Morgan (GDM) transform, that integrates gate resizing, net buffering and De Morgan transformation. ...
Supratik Chakraborty, Rajeev Murgai
AINA
2010
IEEE
16 years 1 days ago
The Cost Effective Pre-processing Based NFA Pattern Matching Architecture for NIDS
—Network Intrusion Detection System (NIDS) is a system which can detect network attacks resulted from worms and viruses on the Internet. An efficient pattern matching algorithm p...
Yeim-Kuan Chang, Chen-Rong Chang, Cheng-Chien Su
FPL
2009
Springer
104views Hardware» more  FPL 2009»
15 years 11 months ago
A multi-layered XML schema and design tool for reusing and integrating FPGA IP
Reconfigurable computing systems remain difficult to use and program. One way to increase design productivity for these systems is through reuse of previously developed and veri...
Adam Arnesen, Nathan Rollins, Michael J. Wirthlin