10718 search results - page 556 / 2144 » On the Circuit Implementation Problem |
192
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ISMVL
2003
IEEE
16 years 13 days ago
2003
IEEE
A new asynchronous data transfer scheme using multiple-valued 2-color 1-phase coding, called a bidirectional data transfer scheme, is proposed for a highperformance and low-power ...
187
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MICRO
2003
IEEE
16 years 13 days ago
2003
IEEE
High-performance caches statically pull up the bitlines in all cache subarrays to optimize cache access latency. Unfortunately, such an architecture results in a significant wast...
174
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MTDT
2003
IEEE
16 years 13 days ago
2003
IEEE
Memory cores (especially SRAM cores) used on a system chip usually come from a memory compiler. Commercial memory compilers have their limitation— a large memory may need to be ...
227
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DAC
2003
ACM
16 years 13 days ago
2003
ACM
We propose in this paper an extension on the Scan Chain Concealment technique to further reduce test time and volume requirement. The proposed methodology stems from the architect...
207
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ISLPED
2003
ACM
16 years 13 days ago
2003
ACM
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...