Sciweavers

10718 search results - page 546 / 2144
» On the Circuit Implementation Problem
Sort
View
ICCAD
2006
IEEE
106views Hardware» more  ICCAD 2006»
16 years 4 months ago
Wire density driven global routing for CMP variation and timing
In this paper, we propose the first wire density driven global routing that considers CMP variation and timing. To enable CMP awareness during global routing, we propose a compac...
Minsik Cho, David Z. Pan, Hua Xiang, Ruchir Puri
ICCAD
2004
IEEE
180views Hardware» more  ICCAD 2004»
16 years 4 months ago
Physical placement driven by sequential timing analysis
Traditional timing-driven placement considers only combinational delays and does not take into account the potential of subsequent sequential optimization steps. As a result, the ...
Aaron P. Hurst, Philip Chong, Andreas Kuehlmann
ICCAD
2002
IEEE
107views Hardware» more  ICCAD 2002»
16 years 4 months ago
Theoretical and practical validation of combined BEM/FEM substrate resistance modeling
In mixed-signal designs, substrate noise originating from the digital part can seriously influence the functionality of the analog part. As such, accurately modeling the properti...
Eelco Schrik, Patrick Dewilde, N. P. van der Meijs
ICCAD
2001
IEEE
163views Hardware» more  ICCAD 2001»
16 years 4 months ago
Predicting the Performance of Synchronous Discrete Event Simulation Systems
In this paper we propose a model to predict the performance of synchronous discrete event simulation. The model considers parameters including the number of active objects per cyc...
Jinsheng Xu, Moon-Jung Chung
FPGA
2010
ACM
243views FPGA» more  FPGA 2010»
16 years 4 months ago
Bit-level optimization for high-level synthesis and FPGA-based acceleration
d hardware design from behavior-level abstraction has drawn wide interest in FPGA-based acceleration and configurable computing research field. However, for many high-level progra...
Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan,...