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DAC
2007
ACM
16 years 8 months ago
On Resolution Proofs for Combinational Equivalence
Modern combinational equivalence checking (CEC) engines are complicated programs which are difficult to verify. In this paper we show how a modern CEC engine can be modified to pr...
Satrajit Chatterjee, Alan Mishchenko, Robert K. Br...
DAC
2005
ACM
16 years 8 months ago
Incremental exploration of the combined physical and behavioral design space
Achieving design closure is one of the biggest headaches for modern VLSI designers. This problem is exacerbated by high-level design automation tools that ignore increasingly impo...
Zhenyu (Peter) Gu, Jia Wang, Robert P. Dick, Hai Z...
DAC
2005
ACM
16 years 8 months ago
An exact jumper insertion algorithm for antenna effect avoidance/fixing
As the process technology enters the nanometer era, reliability has become a major concern in the design and manufacturing of VLSI circuits. In this paper we focus on one reliabil...
Bor-Yiing Su, Yao-Wen Chang
VLSID
2002
IEEE
131views VLSI» more  VLSID 2002»
16 years 7 months ago
Divide-and-Conquer IDDQ Testing for Core-Based System Chips
IDDQ testing has been used as a test technique to supplement voltage testing of CMOS chips. The idea behind IDDQ testing is to declare a chip as faulty if the steady-state current...
C. P. Ravikumar, Rahul Kumar
WSDM
2010
ACM
199views Data Mining» more  WSDM 2010»
16 years 4 months ago
A Sketch-Based Distance Oracle for Web-Scale Graphs
We study the fundamental problem of computing distances between nodes in large graphs such as the web graph and social networks. Our objective is to be able to answer distance que...
Atish Das Sarma, Sreenivas Gollapudi, Marc Najork,...