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» On the Circuit Implementation Problem
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ITC
2003
IEEE
168views Hardware» more  ITC 2003»
16 years 12 days ago
A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy
Embedded memories are among the most widely used cores in current system-on-chip (SOC) implementations. Memory cores usually occupy a significant portion of the chip area, and do...
Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen ...
ISLPED
2003
ACM
95views Hardware» more  ISLPED 2003»
16 years 12 days ago
Power efficient comparators for long arguments in superscalar processors
Traditional pulldown comparators that are used to implement associativeaddressing logic in superscalar microprocessors dissipate energy on a mismatch in any bit position in the co...
Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad ...
GLVLSI
2010
IEEE
171views VLSI» more  GLVLSI 2010»
16 years 7 days ago
Timing-driven variation-aware nonuniform clock mesh synthesis
Clock skew variations adversely affect timing margins, limiting performance, reducing yield, and may also lead to functional faults. Non-tree clock distribution networks, such as ...
Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby...
ISCAS
2002
IEEE
153views Hardware» more  ISCAS 2002»
16 years 2 days ago
Biological learning modeled in an adaptive floating-gate system
We have implemented an aspect of learning and memory in the nervous system using analog electronics. Using a simple synaptic circuit we realize networks with Hebbian type adaptati...
Christal Gordon, Paul E. Hasler
ATS
1998
IEEE
170views Hardware» more  ATS 1998»
15 years 11 months ago
A Ring Architecture Strategy for BIST Test Pattern Generation
This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under tes...
Christophe Fagot, Olivier Gascuel, Patrick Girard,...