10718 search results - page 527 / 2144 » On the Circuit Implementation Problem |
198
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DAC
2005
ACM
15 years 9 months ago
2005
ACM
This paper presents a novel placement algorithm for timing optimization based on a new and powerful concept, which we term differential timing analysis. Recognizing that accurate ...
190
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DAC
2010
ACM
15 years 8 months ago
2010
ACM
This work proposes a new problem of identifying large and tangled logic structures in a synthesized netlist. Large groups of cells that are highly interconnected to each other can...
172
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TCAD
1998
15 years 6 months ago
1998
None of the available minimizers for 2-level hazard-free logic minimization can synthesize very large circuits. This limitation has forced researchers to resort to manual and auto...
194
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CORR
2011
Springer
15 years 2 months ago
2011
Springer
Abstract. Consider a weighted and undirected graph, possibly with self-loops, and its corresponding Laplacian matrix, possibly augmented with additional diagonal elements correspon...
354
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DAC
2011
ACM
14 years 6 months ago
2011
ACM
Clock tree synthesis is one of the most important and challenging problems in 3D ICs. The clock signals have to be delivered by through-silicon vias (TSVs) to different tiers with...