10718 search results - page 526 / 2144 » On the Circuit Implementation Problem |
184
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DAC
2006
ACM
16 years 8 months ago
2006
ACM
As a prevalent constraint, sharp slew rate is often required in circuit design which causes a huge demand for buffering resources. This problem requires ultra-fast buffering techn...
200
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ISPD
2010
ACM
16 years 1 months ago
2010
ACM
Timing-driven placement is a critical step in nanometerscale physical synthesis. To improve design timing on a global scale, net-weight based global timing-driven placement is a c...
223
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ISPD
2004
ACM
16 years 16 days ago
2004
ACM
Modern processors and SoCs require the adoption of poweroriented design styles, due to the implications that power consumption may have on reliability, cost and manufacturability ...
181
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DATE
2002
IEEE
16 years 1 days ago
2002
IEEE
—The dynamic programmable logic array (PLA) style has become popular in designing high-performance microprocessors because of its high speed and predictable routing delay. Howeve...
211
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STOC
1993
ACM
15 years 11 months ago
1993
ACM
Abstract. It is shown that high-order feedforward neural nets of constant depth with piecewisepolynomial activation functions and arbitrary real weights can be simulated for Boolea...